This invention relates to a voltage down converter of a memory device, and more particularly to an internal voltage down converter capable of reducing the effect of an internal voltage variation on an internal circuit.
In general, an internal voltage generation circuit which is referred to as a voltage down converter, generates a reference voltage of a comparator for a final current driver by using a voltage amplifier so as to compensate a level variation of an internal voltage caused by a noise in on-chip circuit operation or a process variation. Herein, the factor of the process variation is a threshold voltage or a saturation current or the like and the noise means a current spike which causes large current flow in a sensing circuit or an input/output circuit. The noise has an effect on an internal voltage circuit and hence causes variation of the predetermined reference voltage.
FIG. 1 shows a block diagram of an internal voltage circuit in the prior art. The internal voltage circuit includes a reference voltage generation portion 110 for stably supplying a constant reference voltage irregardless of an external circumstance variation such as a temperature and an external voltage variation or the like, a reference voltage converting portion 120 for receiving the reference voltage from the reference voltage generation portion 110 to convert a power voltage required according to a normal mode and a stress mode, and a driving portion 130 for receiving the power voltage from the voltage converting portion 120 to generate an internal voltage Vint for driving internal circuitry 140. The internal voltage circuit provides the internal voltage Vint to the internal circuitry as a power voltage.
The reference voltage generation portion 110 includes a first reference voltage generation means 111 for receiving an external voltage to generate a first reference voltage VR1 and a second reference voltage generation means 112 for receiving the first reference voltage generation means 111 to generate a second reference voltage VR2 which is a constant reference voltage and to provide it to the reference voltage conversion portion 120. In the reference voltage generation portion 110, a band-gap reference type generator or a widlar current source type generator as the first reference voltage generation means 111 is typically used.
The second reference voltage generation means 112 includes a comparator 113 which receives the first reference voltage as one input, a first current driver 114 which receives an output signal of the comparator 113 and generates the second reference voltage VR2 and resistors R1 and R2 for voltage-dividing the second reference voltage VR2 and providing the divided voltage Va to another input of the comparator 113.
The second reference voltage VR2 is voltage-divided through the resistors R1 and R2 and the divided voltage VA is fed back to another input of the comparator 113 so that the second reference voltage generation means 112 generates the constant reference voltage VR2.
The reference conversion portion 120 includes a second comparator 121 which the reference voltage VR2 from the reference voltage generation portion 110 is applied to one input thereof and an output of the reference conversion portion 120 is fed back to another input thereof, a second current driver 122 for receiving an output of the second comparator 121 to making a power voltage VR3 suitable to a normal mode as the output of the reference conversion portion 120, a bias generation means 126 for generating a constant bias VST for a stress mode, a third comparator which the bias voltage VST from the bias generation means 126 is applied to one input thereof and the output of the reference conversion portion 120 is fed back to another input thereof, and a third current driver for receiving an output of the third comparator 123 to make a power voltage suitable to a stress mode as the output VR3 of the reference voltage conversion portion 120. In the reference voltage conversion portion 120, the reference numerals 125 and 127 designate a current source, respectively.
In a normal mode, the reference voltage conversion portion 120 receives the reference voltage VR2 from the reference voltage generation portion 110 and the output VR3 thereof as two inputs of the second comparator 121 and generates the power voltage VR3 suitable to a normal mode through the second current driver 122 to the driving portion 130.
In a stress mode, the reference voltage conversion portion 120 receives the constant bias voltage VST from the bias generation means 126 and the output VR3 thereof as two inputs of the third comparator 123 and generates the power voltage VR3 suitable to a normal mode through the third current driver 124 to the driving portion 130. Herein, a normal mode is that a power voltage is 3.3V.+-.10% and a stress mode is that a power voltage is above 1.5.times.3.3V.
In other words, in a normal mode, the second current driver 122 is turned on by the output of the second comparator and the third current driver 124 is turned off by the output of the third comparator 123, so that the output power voltage VR3 is maintained as the output reference voltage VR2 of the reference voltage conversion portion 120. In a stress mode, the second current driver 122 is turned off by the output of the second comparator 121 and the third current driver 124 is turned on by the output of the third comparator 123, so the power voltage VR3 is maintained as the constant bias voltage VST of the bias generation means 126. In general, the constant bias voltage VST is maintained at a value of Vcc(a power voltage)--nVt(herein, n is 2 in general).
The driving portion 130 is for supplying current corresponding to the respective operation modes of the internal circuitry 140. The driving portion 130 includes a fourth comparator 134 which receives the output power voltage VR3 from the reference voltage conversion portion 120 as one input thereof and the internal voltage Vint of the output of the driving portion 130 and a fourth current driver 131 for receiving an output of the fourth comparator 134 to generate the internal voltage Vint to the internal circuitry 140 in a standby mode. The driving portion 130 includes a fifth comparator 135 which receives the output power voltage VR3 from the reference voltage conversion portion 120 as one input thereof and the internal voltage Vint of the output of the driving portion 130 as another input thereof and a fifth current driver 132 for receiving an output of the fifth comparator 135 to generate the internal voltage Vint in an active mode in accordance with a clock ACT.
The fourth current driver 131 is a current driver for a standby mode which is operated when the power voltage Vcc is turned on and a fifth current driver 132 is a current driver for an active mode which is activated by the clock signal ACT. The fourth current driver which a pull down current sink 133 is connected between the output Vint thereof and a ground and the fifth current driver are voltage followers.
The internal circuitry is a on-chip circuit which uses the internal voltage Vint which is dropped from an external voltage Vcc.
However, the prior voltage down circuit has an disadvantage as follows. The resistors R1 and R2 of the reference voltage generation portion 110 is varied with external circumstance such as a noise or a temperature variation in an on-chip circuit operation and the reference voltage generated from the reference voltage generation portion 110 is varied so that the internal circuitry is affected by the reference voltage variation.